US 12,443,354 B2
Boot and initialization techniques for stacked memory architectures
Nathan A. Eckel, Lufkin, TX (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on May 22, 2024, as Appl. No. 18/671,485.
Claims priority of provisional application 63/470,683, filed on Jun. 2, 2023.
Prior Publication US 2024/0402925 A1, Dec. 5, 2024
Prior Publication US 2025/0278206 A2, Sep. 4, 2025
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0632 (2013.01) [G06F 3/0619 (2013.01); G06F 3/0679 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
receiving an initialization command at a common logic block of a first semiconductor die of a memory system, the common logic block coupled with a plurality of interface blocks of the first semiconductor die that are each operable to access, via a respective set of one or more channels, one or more respective memory arrays of one or more second semiconductor dies of the memory system;
outputting, based on receiving the initialization command, an indication of instructions for each interface block of the plurality of interface blocks;
receiving, by each interface block of the plurality of interface blocks, the instructions based on the indication; and
performing, by each interface block of the plurality of interface blocks, one or more respective initialization operations based on each interface block receiving the instructions.