US 12,443,266 B2
Throttling of components using priority ordering
Avinash Ananthakrishnan, Portland, OR (US); and Jeremy Shrall, Portland, OR (US)
Assigned to INTEL CORPORATION, Santa Clara, CA (US)
Filed by INTEL CORPORATION, Santa Clara, CA (US)
Filed on Aug. 23, 2023, as Appl. No. 18/237,337.
Application 18/237,337 is a continuation of application No. 17/405,972, filed on Aug. 18, 2021, granted, now 12,045,114.
Application 17/405,972 is a continuation of application No. 16/144,919, filed on Sep. 27, 2018, granted, now 11,099,628, issued on Aug. 24, 2021.
Prior Publication US 2023/0393646 A1, Dec. 7, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 1/00 (2006.01); G06F 1/28 (2006.01); G06F 1/32 (2019.01); G06F 1/3203 (2019.01); G06F 1/3206 (2019.01); G06F 1/3212 (2019.01); G06F 1/3234 (2019.01); G06F 1/324 (2019.01); G06F 1/3296 (2019.01); G06F 9/30 (2018.01)
CPC G06F 1/3296 (2013.01) [G06F 1/28 (2013.01); G06F 1/32 (2013.01); G06F 1/3203 (2013.01); G06F 1/3206 (2013.01); G06F 1/3212 (2013.01); G06F 1/3234 (2013.01); G06F 1/324 (2013.01); G06F 9/30101 (2013.01); G06F 9/30 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A non-transitory computer-readable storage medium to store instructions that, when executed by a processor, cause the processor to:
receive a plurality of throttling priorities for a corresponding plurality of hardware components;
determine a sequence in which hardware components of the corresponding plurality of hardware components are to be throttled, based on the plurality of throttling priorities; and
respectively assign the plurality of throttling priorities to the corresponding plurality of hardware components, based on input received from software executed on the processor, the software receiving the input including both of an operating system (OS) and a user interface,
wherein the corresponding plurality of hardware components include a graphics processing unit (GPU) and a central processing unit (CPU), the GPU to be associated with a first throttling priority of the plurality of throttling priorities and the CPU to be associated with a second throttling priority of the plurality of throttling priorities, and
wherein the GPU is throttled prior to the CPU in response to the second throttling priority being different from the first throttling priority.