	US 12,443,264 B2
	Shallow hibernate power state
Deping He, Boise, ID (US); Nadav Grosz, Broomfield, CO (US); and Jonathan S. Parry, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Mar. 6, 2024, as Appl. No. 18/597,462.
Application 18/597,462 is a continuation of application No. 17/648,394, filed on Jan. 19, 2022, granted, now 11,934,252.
Claims priority of provisional application 63/162,140, filed on Mar. 17, 2021.
Prior Publication US 2024/0329721 A1, Oct. 3, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 1/32 (2019.01); G06F 1/3234 (2019.01); G06F 1/3287 (2019.01)

CPC G06F 1/3275 (2013.01) [G06F 1/3287 (2013.01)]

20 Claims

1. A memory system, comprising:

one or more memory arrays; and

processing circuitry coupled with the one or more memory arrays and configured to cause the memory system to:

read a value from a register while operating in a first power state;

disable a first timer in response to reading the value from the register;

transition from the first power state to a second power state in response to reading the value from the register;

initiate a second timer in response to transitioning from the first power state to the second power state;

determine the second timer satisfies a threshold in response to initiating the second timer; and

transition, in accordance with determining the second timer satisfies the threshold, from the second power state to a third power state.