US 12,443,218 B2
Clock and data recovery circuit module, memory storage device and signal calibration method
Yu-Chiang Liao, Miaoli County (TW); and Jen-Chu Wu, New Taipei (TW)
Assigned to PHISON ELECTRONICS CORP., Miaoli (TW)
Filed by PHISON ELECTRONICS CORP., Miaoli (TW)
Filed on Apr. 16, 2024, as Appl. No. 18/637,397.
Claims priority of application No. 113110183 (TW), filed on Mar. 19, 2024.
Prior Publication US 2025/0298433 A1, Sep. 25, 2025
Int. Cl. G06F 1/12 (2006.01); G06F 1/08 (2006.01); H04L 7/02 (2006.01)
CPC G06F 1/12 (2013.01) [G06F 1/08 (2013.01); H04L 7/02 (2013.01)] 24 Claims
OG exemplary drawing
 
1. A clock and data recovery circuit module, comprising:
a first detector;
a second detector;
a clock signal generation circuit, coupled to the first detector and the second detector; and
a phase adjustment circuit, coupled to the clock signal generation circuit,
wherein the first detector is configured to receive a reference clock signal and a first clock signal and detect a first difference value between the reference clock signal and the first clock signal,
the second detector is configured to receive a data signal and a second clock signal and detect a second difference value between the data signal and the second clock signal,
the clock signal generation circuit is configured to generate the first clock signal and the second clock signal according to one of the first difference value and the second difference value, a frequency of the second clock signal is higher than a frequency of the first clock signal, and
during a time period in which the first detector and the second detector are worked, the phase adjustment circuit is configured to adjust one of the reference clock signal, the first clock signal and the second clock signal according to the second difference value.