US 12,443,216 B2
Generation of clock waveforms based on decoded instructions for more efficient power management in high-speed processors
James David Sproch, Monte Sereno, CA (US)
Assigned to Groq, Inc., San Jose, CA (US)
Filed by Groq, Inc., Mountain View, CA (US)
Filed on May 24, 2023, as Appl. No. 18/323,188.
Claims priority of provisional application 63/502,567, filed on May 16, 2023.
Prior Publication US 2024/0385641 A1, Nov. 21, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 1/08 (2006.01)
CPC G06F 1/08 (2013.01) 20 Claims
OG exemplary drawing
 
1. A digital circuit for clock waveform synthesis for each individual instruction or operational cycle of a processor, comprising:
an instruction control unit (ICU) that supplies instructions to control the generation of clock signals;
a clock pulse synthesis (CPS) controller connected to the ICU, wherein the CPS controller decodes the instructions supplied from the ICU and generates clock waveform parameter signals;
wherein a CPS circuit comprises the CPS controller and a waveform generator that produces waveforms based on the clock waveform parameter signals;
a duration logic block that uses the clock waveform parameter signals supplied by the CPS controller and preloads values for the waveform generator;
a shift register that is clocked by a high frequency clock that operates at a frequency that is higher than a nominal processor clock frequency, wherein the high frequency clock is generated by a phase-locked loop circuit on the processor;
wherein the shift register is comprised of one or more toggle flip-flop registers that are initialized by using the duration logic block and the clock waveform parameter signals supplied by the CPS controller; and
a bypass multiplexer that is connected, via an output of the bypass multiplexer, to the processor, wherein the bypass multiplexer is supplied with a first clock signal that is output from the shift register and a second clock signal from a phase locked loop that provides the high frequency clock.