US 12,443,088 B2
Electronic paper and display device
Gang Hua, Beijing (CN); Min Wang, Beijing (CN); Shaokai Su, Beijing (CN); Dong Wang, Beijing (CN); Zhe Wang, Beijing (CN); Shaobo Li, Beijing (CN); Meng Gong, Beijing (CN); Jintang Hu, Beijing (CN); Jinghao Liu, Beijing (CN); Liangliang Pan, Beijing (CN); Guangquan Wang, Beijing (CN); Liguang Deng, Beijing (CN); and Pengkai Fan, Beijing (CN)
Assigned to Beijing BOE Optoelectronics Technology Co., Ltd., Beijing (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
Filed by Beijing BOE Optoelectronics Technology Co., Ltd., Beijing (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
Filed on Nov. 29, 2021, as Appl. No. 17/536,870.
Claims priority of application No. 202120365937.4 (CN), filed on Feb. 8, 2021.
Prior Publication US 2022/0252955 A1, Aug. 11, 2022
Int. Cl. G02F 1/1676 (2019.01); G02F 1/167 (2019.01)
CPC G02F 1/1676 (2019.01) [G02F 1/167 (2013.01)] 18 Claims
OG exemplary drawing
 
1. An electronic paper, comprising: an array substrate and a cover plate facing each other, as well as an electrophoretic layer disposed between the array substrate and the cover plate, wherein the array substrate comprises:
a base;
a pixel electrode and a thin film transistor that are disposed on the base, wherein the pixel electrode is connected to the thin film transistor, and the thin film transistor comprises an active layer and a source/drain layer lapped with the active layer; and
a shielding electrode disposed between the pixel electrode and the source/drain layer, wherein the shielding electrode is insulated from the pixel electrode and the source/drain layer; and an orthographic projection of the active layer on the base is within an orthographic projection of the shielding electrode on the base, and is within an orthographic projection of the pixel electrode on the base,
wherein the orthographic projection of the shielding electrode on the base and the orthographic projection of the pixel electrode on the base has an overlapped region, and the shielding electrode and the pixel electrode are configured to form a storage capacitor,
the array substrate further comprises: a first insulating layer disposed between the pixel electrode and the shielding electrode, and a second insulating layer disposed between the source/drain layer and the shielding electrode; and
the source/drain layer comprises a first electrode and a second electrode,
wherein the first insulating layer is provided with a first via hole, the second insulating layer is provided with a second via hole communicated with the first via hole, and the pixel electrode is connected to the first electrode through the first via hole and the second via hole.