US 12,443,081 B2
Array substrate and method for manufacturing same, display panel, and display device
Yadong Zhang, Beijing (CN); Ting Li, Beijing (CN); Bo Wu, Beijing (CN); and Xiongcan Zuo, Beijing (CN)
Assigned to CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., Sichuan (CN); and BEIJING BOE TECHNOLOGY DEVELOPMENT CO., LTD., Beijing (CN)
Appl. No. 18/686,877
Filed by Chengdu BOE Optoelectronics Technology Co., Ltd., Sichuan (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
PCT Filed Oct. 27, 2022, PCT No. PCT/CN2022/128057
§ 371(c)(1), (2) Date Feb. 27, 2024,
PCT Pub. No. WO2024/087117, PCT Pub. Date May 2, 2024.
Prior Publication US 2025/0130471 A1, Apr. 24, 2025
Int. Cl. G09G 3/36 (2006.01); G02F 1/1362 (2006.01); G02F 1/1368 (2006.01)
CPC G02F 1/136286 (2013.01) [G02F 1/1368 (2013.01); G09G 3/3674 (2013.01); G09G 2300/0408 (2013.01); G09G 2300/0426 (2013.01)] 16 Claims
OG exemplary drawing
 
1. An array substrate, comprising a substrate; wherein
the substrate comprises a display region and a peripheral region surrounding the display region, the display region comprising a plurality of pixel regions arranged in arrays;
the array substrate further comprises a plurality of GOA units and a plurality of gate lines, wherein the plurality of GOA units are arranged along a first direction, the peripheral region comprises a data pad (DP) region and a data pad opposite (DPO) region that are arranged opposite to each other along a second direction on two sides of the display region, the plurality of GOA units are within the DPO region, the plurality of gate lines are within the display region, and the plurality of GOA units are electrically connected to the plurality of gate lines, the first direction being intersected with the second direction; and
in the display region, the array substrate further comprises a gate layer, a gate insulator layer, a source-drain layer, a protection layer, and a common electrode layer that are successively stacked on the substrate, the common electrode layer comprising a gate connection line,
wherein the plurality of gate lines comprise a plurality of first gate lines and a plurality of second gate lines, wherein extension directions of the plurality of first gate lines are consistent with the second direction, extension directions of the plurality of second gate lines are consistent with the first direction, and the plurality of second gate lines are connected to the plurality of GOA units respectively by the plurality of first gate lines; and
the plurality of first gate lines are disposed in the source-drain layer, the plurality of second gate lines are disposed in the gate layer, the plurality of first gate lines are connected to the gate connection line through a first via in the protection layer, and the plurality of second gate lines are connected to the gate connection line through a second via in the gate insulator layer and the protection layer.