US 12,443,080 B2
Active matrix substrate and display device
Hitoshi Takahata, Kameyama (JP); Tohru Daitoh, Kameyama (JP); Tetsuo Kikuchi, Kameyama (JP); Masahiko Suzuki, Kameyama (JP); and Setsuji Nishimiya, Kameyama (JP)
Assigned to SHARP DISPLAY TECHNOLOGY CORPORATION, Kameyama (JP)
Filed by Sharp Display Technology Corporation, Kameyama (JP)
Filed on Jun. 20, 2023, as Appl. No. 18/211,805.
Claims priority of application No. 2022-100162 (JP), filed on Jun. 22, 2022.
Prior Publication US 2023/0418123 A1, Dec. 28, 2023
Int. Cl. G02F 1/1362 (2006.01); G02F 1/1368 (2006.01); H10D 86/40 (2025.01); H10D 86/60 (2025.01)
CPC G02F 1/136286 (2013.01) [G02F 1/1368 (2013.01); H10D 86/423 (2025.01); H10D 86/441 (2025.01); H10D 86/60 (2025.01)] 14 Claims
OG exemplary drawing
 
1. An active matrix substrate comprising:
a plurality of pixel regions arranged in a matrix;
a substrate;
a thin film transistor (TFT) supported by the substrate and provided corresponding to each of the plurality of pixel regions, the TFT including an oxide semiconductor layer, a gate insulating layer provided on the oxide semiconductor layer, and a gate electrode facing the oxide semiconductor layer with the gate insulating layer interposed therebetween;
a plurality of gate lines extending in a row direction and formed of the same conductive film as the gate electrode;
an interlayer insulating layer covering the gate electrode and the plurality of gate lines;
a plurality of source lines extending in a column direction and provided on the interlayer insulating layer;
an upper insulating layer covering the plurality of source lines;
an organic insulating layer provided on the upper insulating layer;
a display region and a peripheral region located around the display region;
a gate metal layer including the gate electrode and the plurality of gate lines; and
a source metal layer including the plurality of source lines; wherein
the interlayer insulating layer includes:
a first layer formed of silicon oxide,
a second layer provided on the first layer and formed of silicon nitride, and
a third layer provided on the second layer and formed of silicon oxide;
the organic insulating layer and the upper insulating layer include an opening provided to extend through both the organic insulating layer and the upper insulating layer; and
the opening overlaps, in the peripheral region, an intersection region in which the gate metal layer and the source metal layer overlap each other with the interlayer insulating layer interposed therebetween.