US 12,442,995 B2
Photonic integrated circuit and package structure
Tsung-Yuan Yu, Taipei (TW); Hung-Yi Kuo, Taipei (TW); Cheng-Chieh Hsieh, Tainan (TW); Hao-Yi Tsai, Hsinchu (TW); Chung-Ming Weng, Taichung (TW); Hua-Kuei Lin, Hsinchu (TW); and Che-Hsiang Hsu, Taichung (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Sep. 21, 2023, as Appl. No. 18/471,323.
Application 18/471,323 is a continuation of application No. 17/206,130, filed on Mar. 19, 2021, granted, now 11,809,000.
Prior Publication US 2024/0012213 A1, Jan. 11, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G02B 6/42 (2006.01); G02B 6/12 (2006.01); H01L 23/00 (2006.01); H01L 25/16 (2023.01)
CPC G02B 6/4251 (2013.01) [G02B 6/12002 (2013.01); G02B 6/12004 (2013.01); H01L 25/167 (2013.01); G02B 6/12 (2013.01); G02B 2006/12061 (2013.01); G02B 2006/121 (2013.01); H01L 23/562 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A photonic integrated circuit having a central region and a peripheral region surrounding the central region, comprising:
a semiconductor layer;
a seal ring structure disposed on the semiconductor layer, wherein the seal ring structure is located in the peripheral region and has a plurality of recesses recessing towards the central region from a top view, the seal ring structure is a continuous structure from the top view, and the seal ring structure exhibits a comb shape from the top view; and
a plurality of silicon waveguides embedded in the semiconductor layer, wherein the semiconductor layer covers top surfaces of the plurality of the silicon waveguides.