US 12,442,859 B1
Directional control of scan capture through shared wrapper cells
Veerabhadra Rao Vasa, Bengaluru (IN)
Assigned to Google LLC, Mountain View, CA (US)
Filed by Google LLC, Mountain View, CA (US)
Filed on Jun. 6, 2024, as Appl. No. 18/736,001.
Int. Cl. G01R 31/3177 (2006.01); G01R 31/28 (2006.01); G01R 31/317 (2006.01); G01R 31/3185 (2006.01)
CPC G01R 31/3177 (2013.01) [G01R 31/2815 (2013.01); G01R 31/31713 (2013.01); G01R 31/31724 (2013.01); G01R 31/318533 (2013.01); G01R 31/318597 (2013.01)] 19 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) for directional control of scan capture through shared wrapper cells comprising:
a first input node coupled with an in-test mode test data register (TDR);
a second input node coupled with a sync interface TDR;
a third input node coupled with a scan enable pin;
a fourth input node coupled with an ex-test mode TDR;
a first output node with an input shared wrapper cell;
a second output node coupled with an output shared wrapper cell;
a control circuit comprising:
a NOT gate having an input and an output, the input coupled with the sync interface TDR via the second input node;
an OR gate having a first input, a second input, and an output, the first input coupled with the output of the NOT gate and the second input coupled with the scan enable pin via the third input node;
a first AND gate having a first input, a second input, and an output, the first input of the first AND gate coupled with the in-test mode TDR via the first input node, the second input of the first AND gate coupled with the output of the OR gate, and the output of the first AND gate coupled with the input shared wrapper cell via the first output node; and
a second AND gate having a first input, a second input, and an output, the first input of the second AND gate coupled with the output of the OR gate and the second input of the second AND gate coupled with the ex-test mode TDR via the fourth input node, and the output of the second AND gate coupled with the output shared wrapper cell via the second output node.