| CPC G01R 31/31719 (2013.01) [G01R 31/31727 (2013.01); G01R 31/318544 (2013.01)] | 15 Claims |
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1. A semiconductor integrated circuit configured to receive a test scan input signal, a test clock signal, and a test mode signal and to output a secure scan output signal, the semiconductor integrated circuit comprising:
a secure key circuit configured to generate a plurality of delay input signals, each of which having a different delay with respect to the test scan input signal, and to generate an input key signal by capturing a logic level of each of the plurality of delay input signals in response to each rising edge of the test clock signal, such that an input key of the input key signal is varied at each rising edge of the test clock signal;
a key comparator configured to generate a verification result signal indicating whether the input key is identical with a reference key;
a chip configured to generate a scan output signal based on the test scan input signal;
a scan output remapper configured to receive the scan output signal, to output an unobfuscated scan output signal as the secure scan output signal based on the verification result signal indicating that the input key of the input key signal is identical with the reference key, to obfuscate the scan output signal based on the verification result signal indicating that the input key of the input key signal is different from the reference key, and to output the obfuscated scan output signal as the secure scan output signal; and
a secure scan controller configured to control the secure key circuit, the key comparator, the chip, and the scan output remapper.
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