US 12,442,855 B1
Built-in circuit for testing process and layout effects of an integrated circuit die
Eric D. Hunt-Schroeder, Essex Junction, VT (US); Steven Harley Lamphier, Colchester, VT (US); Dale E. Pontius, Colchester, VT (US); and Christopher Kanyuck, Lakeland, FL (US)
Assigned to MARVELL ASIA PTE LTD, Singapore (SG)
Filed by Marvell Asia Pte Ltd, Singapore (SG)
Filed on Apr. 21, 2023, as Appl. No. 18/304,501.
Claims priority of provisional application 63/335,259, filed on Apr. 27, 2022.
Int. Cl. G01R 31/28 (2006.01); G01R 31/307 (2006.01); H01L 21/66 (2006.01)
CPC G01R 31/2884 (2013.01) [H01L 22/34 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit device comprising:
functional circuitry including transistors;
testing circuitry configured to test effects of different layouts of the functional circuitry, relative to physical features of the integrated circuit device, on operation of the transistors, the testing circuitry comprising:
at least one first test circuit having a first layout relationship relative to the physical features of the integrated circuit device,
at least one second test circuit having a second layout relationship, different from the first layout relationship, relative to the physical features of the integrated circuit device, and
sensing circuitry configured to read outputs of (a) the at least one first test circuit and (b) the at least one second test circuit; and
imbalance circuitry configured to apply compensation to the functional circuitry to compensate for an imbalance, between the output of the at least one first test circuit and the output of the at least one second test circuit, resulting from a difference between the first layout relationship and the second layout relationship.