| CPC G01R 31/2851 (2013.01) [G01R 31/31727 (2013.01); H03K 3/037 (2013.01); H03K 5/00006 (2013.01); H03K 19/20 (2013.01)] | 17 Claims |
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1. A test aid unit comprising:
a clock signal divider configured to generate a ½ divided clock signal, a ¼ divided clock signal, and a ⅛ divided clock signal, which are synchronized with a reference clock signal, by using a plurality of reset signals, the reference clock signal, and a reference clock bar signal having a phase opposite to that of the reference clock signal;
an integrated digital logic circuit configured to operate in response to a plurality of test control signals received from automatic test equipment, and to generate a driver enable signal, a data strobe signal, a data clock signal, and a check result signal;
a multi-channel transmitter configured to convert transmission rates of the data strobe signal and the data clock signal in parallel form into a transmission rate corresponding to a data processing rate of a device under test in response to the reference clock signal, the ½ divided clock signal, the ¼ divided clock signal, and the ⅛ divided clock signal, and to transmit the converted signals to the device under test; and
a multi-channel receiver configured to convert received data signals in serial form received from the device under test into parallel data in response to the reference clock signal, the ½ divided clock signal, the ¼ divided clock signal, and the ⅛ divided clock signal, and to transmit the parallel data to the integrated digital logic unit,
wherein cycles of the ½ divided clock signal, the ¼ divided clock signal, and the ⅛ divided clock signal are ½ times, ¼ times, and ⅛ times a cycle of the reference clock signal, respectively.
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