US 12,442,850 B2
Semiconductor device configured for gate dielectric monitoring
Edward John Coyne, Athenry (IE); John P. Meskell, Castleconnell (IE); Colm Patrick Heffernan, Limerick (IE); Mark Forde, Nenagh (IE); and Shane Geary, Sixmilebridge (IE)
Assigned to Analog Devices International Unlimited Company, County Limerick (IE)
Filed by Analog Devices International Unlimited Company, County Limerick (IE)
Filed on Jun. 5, 2024, as Appl. No. 18/734,307.
Application 18/734,307 is a continuation of application No. 16/996,458, filed on Aug. 18, 2020, granted, now 12,032,014.
Claims priority of provisional application 62/897,729, filed on Sep. 9, 2019.
Prior Publication US 2025/0004034 A1, Jan. 2, 2025
Int. Cl. G01R 31/26 (2020.01); H10D 10/60 (2025.01); H10D 30/65 (2025.01); H10D 62/17 (2025.01); H10D 84/40 (2025.01)
CPC G01R 31/2608 (2013.01) [H10D 10/60 (2025.01); H10D 30/65 (2025.01); H10D 62/393 (2025.01); H10D 84/409 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A method of monitoring a semiconductor device, the method comprising:
providing a semiconductor device comprising a metal-oxide-semiconductor (MOS) transistor comprising a source, a drain, a gate, and a backgate region, the semiconductor device further comprising a bipolar junction transistor (BJT) integrated on a same substrate with the MOS transistor, wherein a first well of a first dopant type forms the backgate region of the MOS transistor and serves as a base of the BJT and is independently accessible for activating the BJT, wherein the MOS transistor comprises an extended drain drift region comprising a second well of a second dopant type, opposite the first dopant type, between and abutting the drain and the first well; and
operating the semiconductor device in an accelerated stress mode in which a source voltage (Vs) applied to the source and a backgate voltage (Vbg) applied to the backgate region are different voltages.