US 12,442,842 B2
Test devices and systems that utilize efficient test algorithms to evaluate devices under test
Jungmin Bak, Suwon-si (KR); Junyoung Ko, Suwon-si (KR); and Changhwi Park, Suwon-si (KR)
Assigned to Samsung Electronics Co., Ltd., (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Feb. 9, 2023, as Appl. No. 18/166,656.
Claims priority of application No. 10-2022-0116650 (KR), filed on Sep. 15, 2022.
Prior Publication US 2023/0408554 A1, Dec. 21, 2023
Int. Cl. G01R 19/00 (2006.01); G01R 19/165 (2006.01); G11C 29/50 (2006.01)
CPC G01R 19/0038 (2013.01) [G01R 19/16552 (2013.01); G11C 29/50004 (2013.01); G11C 2029/5004 (2013.01); G11C 2029/5006 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A test device comprising:
a power supply circuit including a power voltage pin, said power supply circuit configured to supply an input voltage through the power voltage pin to a memory device under test;
a current sensor configured to measure a current flowing to the memory device through the power voltage pin:
a clock driver configured to provide a clock signal to the memory device through a clock pin; and
a test controller configured to: transmit a command signal to the memory device, measure a first current flowing to the memory device through the power voltage pin a first period of the clock signal after transmitting the command signal, measure a second current flowing to the memory device through the power voltage pin in a second period of the clock signal, which is different from the first period of the clock signal, and determine whether the memory device is operating to satisfy a normal timing parameter based on the measured first current and the measured second current.