| CPC G01R 19/0023 (2013.01) [H02J 50/10 (2016.02); H03F 3/45475 (2013.01)] | 20 Claims |

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1. An integrated circuit comprising:
a first resistor coupled between a first node and a second node; wherein the first resistor has a first resistance (Rs); wherein the first resistor is configured to carry a first current (Isns) across the first resistor when the first node has a first voltage (Vrect) and the second node has a second voltage (Vmid);
a first amplifier including a first input coupled to the first node and a second input coupled to the second node; the first amplifier configured to output a third voltage (Vo);
a second resistor and a third resistor; wherein the second resistor and the third resistor each have a second resistance (Rt); wherein the second resistor is coupled between the first node and a first input of the first amplifier; wherein the third resistor is coupled between the second node and a second input of the first amplifier;
a plurality of switches for measuring an offset; and
a second amplifier including a third input coupled to the first node and a fourth input coupled to the second node; the second amplifier configured to output a fourth voltage (Van).
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