US 12,442,742 B2
Test structures to determine integrated circuit bonding energies and methods of making and using the same
Yu-Sheng Lin, Zhubei (TW); Jyun-Lin Wu, Hsinchu (TW); Yao-Chun Chuang, Hsinchu (TW); and Chin-Fu Kao, Taipei (TW)
Assigned to Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed on Apr. 20, 2023, as Appl. No. 18/303,647.
Claims priority of provisional application 63/406,755, filed on Sep. 15, 2022.
Prior Publication US 2024/0094104 A1, Mar. 21, 2024
Int. Cl. G01N 3/20 (2006.01); G01N 19/04 (2006.01)
CPC G01N 3/20 (2013.01) [G01N 19/04 (2013.01); G01N 2203/0064 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An interfacial bonding test structure, comprising:
a first substrate having a first planar surface;
a second substrate have a second planar surface that is parallel to the first planar surface;
a first semiconductor die and a second semiconductor die each located between the first substrate and the second substrate such that the first substrate, the second substrate, the first semiconductor die, and the second semiconductor die, form a sandwich structure, wherein the first semiconductor die and the second semiconductor die are located adjacent to one another and are laterally displaced from one another by a first separation along a direction parallel to the first planar surface and the second planar surface;
a first adhesive that bonds the first semiconductor die and the second semiconductor die to the first substrate;
a second adhesive that that bonds the first semiconductor die and the second semiconductor die to the second substrate; and
a notch formed in the second substrate, wherein the notch extends into the second substrate such that an area of the notch is overlapping with an area of the first separation in a plan view.