US 12,442,668 B2
Low power capacitor sensor array
Krishna Shivaram, Torrance, CA (US); Phung N. Phan, Simi Valley, CA (US); Rodrigo Cuba, Los Angeles, CA (US); and Bronson Riley Edralin, Carson, CA (US)
Assigned to Raytheon Company, Arlington, VA (US)
Filed by Raytheon Company, Arlington, VA (US)
Filed on Jul. 11, 2023, as Appl. No. 18/350,043.
Application 18/350,043 is a continuation in part of application No. 18/169,417, filed on Feb. 15, 2023.
Prior Publication US 2025/0003772 A1, Jan. 2, 2025
Int. Cl. G01D 5/24 (2006.01); G01R 27/26 (2006.01)
CPC G01D 5/24 (2013.01) [G01R 27/2605 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A capacitive sensor, comprising:
a driver device having a first input configured to receive a clock signal, a second input configured to receive a charging voltage, a third input configured to receive a common-mode voltage, and an output;
a first capacitor configured to be sensed, having a first terminal connected to the output of the driver device and a second terminal; and
a receiver device having a first input configured to receive the clock signal, a second input connected to the second terminal of the first capacitor, and a third input configured to receive the common mode voltage, wherein the receiver comprises a temperature-compensated analog-to-digital converter (ADC) having an input connected to the output of an operational amplifier,
wherein the temperature-compensated ADC comprises a voltage reference generator having an input for receiving an analog power supply voltage (AVDD) and an output configured to provide a constant voltage independent of temperature and supply voltage, and
wherein the voltage reference generator comprises:
a comparator comprising a first terminal connected to AVDD, a second terminal connected to a ground potential, a negative input, a positive input, and an output;
a first p-channel Metal Oxide Semiconductor (MOS) transistor comprising a source terminal connected to AVDD, a gate terminal connected to tile output of the comparator, and a drain terminal connected to the positive input of the comparator;
a second p-channel MOS transistor comprising a source terminal connected to AVDD, a gate terminal connected to the output of the comparator, and a drain terminal connected to the negative input of the comparator;
a third p-channel MOS transistor comprising a source terminal connected to AVDD, a gate terminal connected to the output of the comparator, and a drain terminal;
a first variable resistor comprising a first resistive terminal connected to the drain terminal of the first p-channel transistor, a second resistive terminal connected to the ground potential, and an adjustment terminal for receiving a digital conversely-proportional-to-absolute-temperature (CTAT) voltage adjustment signal CTAT_ADJ<M:0>;
a second variable resistor comprising a first resistive terminal connected to the drain terminal of the second p-channel transistor, a second resistive terminal, and an adjustment terminal for receiving a digital proportional-to-absolute-temperature (PTAT) voltage adjustment signal PTAT_ADJ<N:0>;
a third variable resistor comprising a first resistive terminal connected to the drain terminal of the second p-channel transistor, a second resistive terminal connected to the ground potential, and an adjustment terminal for receiving the digital CTAT voltage adjustment signal CTAT_ADJ<M:0>;
a fourth variable resistor comprising a first resistive terminal connected to the drain terminal of the third p-channel transistor, a second resistive terminal connected to the ground potential, and an adjustment terminal for receiving a digital resistive adjustment signal R_ADJ<P:0>;
a first diode comprising an anode connected to the drain of the first p-channel MOS transistor and a cathode connected to the ground potential; and
a second diode comprising an anode connected to the second resistive terminal of the second variable resistor and a cathode connected to the ground potential, wherein the second diode comprises an area K times larger than the first diode.