| CPC E21B 47/12 (2013.01) [E21B 44/06 (2013.01); H04L 1/0041 (2013.01); H04L 1/0045 (2013.01); H04L 1/0063 (2013.01)] | 4 Claims |
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1. A method of encoding and decoding a downlink instruction based on mud flow rate, comprising: an encoding method and a decoding method, wherein the encoding method and the decoding method are for transmitting and receiving instructions by controlling the mud flow rate during drilling process;
wherein the decoding method comprises the following steps:
S1, when the downlink instruction is not started, continuously collecting voltage values, calculating and comparing average values of the voltage values, and performing counting when a condition for counter_0 to be incremented by 1 is met, wherein the condition for the counter_0 to be incremented by 1 is met when an average value of a current set of 10 collected voltage values is less than 10% of an average value of a previous set of 10 collected voltage values;
S2, starting the downlink instruction when the counter_0 is greater than or equal to 3, capturing a first symbol “0” of a synchronization header, resetting the counter_0 to zero and ceasing an increment operation of the counter_0, continuously collecting the voltage values for comparison, performing counting when a condition for counter_1 to be incremented by 1 is met, simultaneously starting a timer to record a time, and recording and storing a pulse width duration of the first symbol “0” of the synchronization header, wherein the condition for the counter_1 to be incremented by 1 is met when the average value of the current set of 10 collected voltage values is greater than 10% of the average value of the previous set of 10 collected voltage values;
S3, capturing a second symbol “1” of the synchronization header when the counter_1 is greater than or equal to 3, resetting the counter_1 to zero and ceasing an increment operation of the counter_1, continuously collecting the voltage values for comparison, performing counting when the condition for the counter_0 to be incremented by 1 is met, simultaneously starting the timer to record the time, and recording and storing a pulse width duration of the second symbol “1” of the synchronization header;
S4, repeating the above S2 and S3 until a capture of 6-bit symbols of the synchronization header is completed, calculating an average of 6 pulse widths saved from the aforementioned steps, recording 90% of the average of the 6 pulse widths as time_down and 110% of the average of the 6 pulse widths as time_up, and using an interval [time_down, time_up] as a pulse width judgment interval for subsequent data segment symbols;
S5, based on a voltage change rate-based symbol judgment method, determining a “0” or “1” state of each bit in a data segment by comparing relative changes of average values of the mud flow rate over continuous time periods, capturing a first symbol “0” of a command code when the counter_0 is greater than or equal to 3, starting the timer to record the time, simultaneously resetting the counter_0 to zero and ceasing the increment operation of the counter_0, continuously collecting the voltage values for comparison, and performing counting when the condition for the counter_1 to be incremented by 1 is met;
S6, stopping the timer until the counter_1 is greater than or equal to 3, recording a total counting time as time_total, determining a number of symbols “0” of the command code based on the pulse width judgment interval obtained in S4, where the number of the symbols “0” of the command code is an integer within an interval [time_total/time_up, time_total/time_down]; and simultaneously resetting the counter_1 to zero and ceasing the increment operation of the counter_1, continuously collecting the voltage values for comparison, and performing counting when the condition for the counter_0 to be incremented by 1 is met;
S7, repeating the above S5 and S6 until a capture of 4-bit symbols of the command code is completed, and calculating an even parity value;
S8, capturing 3-bit symbols of a data length to obtain a subsequent data length, and updating the even parity value; wherein the capturing the 3-bit symbols of the data length to obtain the subsequent data length comprises:
S81, capturing a first symbol of the data length when the counter_0 or the counter_1 is greater than or equal to 3, starting the timer to record the time, simultaneously resetting the counter_0 or the counter_1 to zero and ceasing the increment operation of the counter_0 or the counter_1, continuously collecting the voltage values for comparison, and performing counting when the condition for the counter_1 or the counter_0 to be incremented by 1 is met;
S82, stopping the timer until the counter_1 or the counter_0 is greater than or equal to 3, recording the total counting time as the time_total, determining a number of symbols “0” or “1” of the data length based on the pulse width judgment interval obtained in S4, where the number of the symbols “0” or “1” of the data length is an integer within the interval [time_total/time_up, time_total/time_down]; and simultaneously resetting the counter_1 or the counter_0 to zero and ceasing the increment operation of the counter_1 or the counter_0, continuously collecting the voltage values for comparison, and performing counting when the condition for the counter_0 or the counter_1 to be incremented by 1 is met; and
S83, repeating the above S81 and S82 until a capture of the 3-bit symbols of the data length is completed;
S9, capturing N-bit symbols of the data segment, and completing a capture of the symbols of the data segment when a number of captured symbols is equal to the subsequent data length obtained in S8; wherein the capturing the N-bit symbols of the data segment comprises:
S91, capturing a first symbol of the data segment when the counter_0 or the counter_1 is greater than or equal to 3, starting the timer to record the time, simultaneously resetting the counter_0 or the counter_1 to zero and ceasing the increment operation of the counter_0 or the counter_1, continuously collecting the voltage values for comparison, and performing counting when the condition for the counter_1 or the counter_0 to be incremented by I is met;
S92, stopping the timer until the counter_1 or the counter_0 is greater than or equal to 3, recording the total counting time as the time_total, determining a number of symbols “0” or “1” of the data length based on the pulse width judgment interval obtained in S4, where the number of the symbols “0” or “1” of the data length is an integer within the interval [time_total/time_up, time_total/time_down]; and simultaneously resetting the counter_1 or the counter_0 to zero and ceasing the increment operation of the counter_1 or the counter_0, continuously collecting the voltage values for comparison, and performing counting when the condition for the counter_0 or the counter_1 to be incremented by 1 is met; and
S93, repeating the above S91 and S92 until a capture of the N-bit symbols of the data segment is completed; and
S10, capturing a 1-bit symbol of an even parity bit, and determining whether the 1-bit symbol of the even parity bit is equal to the even parity value; and sending the instructions to a rotary steerable system when the 1-bit symbol of the even parity bit is equal to the even parity value, and returning to S1 when the 1-bit symbol of the even parity bit is not equal to the even parity value;
wherein the voltage change rate-based symbol judgment method comprises:
continuously performing an operation of collecting the voltage values every 50 milliseconds (ms) downhole and calculating an average value from 10 collected voltage values over 500 ms as a set;
comparing the average value of the current set with the average value of the previous set:
when the average value of the current set is greater than or less than the average value of the previous set by 10%, determining the current set as a valid set; increasing the counter_1 by 1 in response to the average value of the current set being greater than the average value of the previous set; and increasing the counter_0 by 1 in response to the average value of the current set being less than the average value of the previous set;
comparing an average value of a next set with the average value of the current set:
when the average value of the next set is greater than or less than the average value of the current set by 10%, determining the next set as a valid set; increasing the counter_1 by 1 in response to the average value of the next set being greater than the average value of the current set; and increasing the counter_0 by 1 in response to the average value of the next set being less than the average value of the current set; and
when the counter_0 or the counter_1 is increased continuously for 3 times, that is, the counter_0 is greater than or equal to 3 or the counter_1 is greater than or equal to 3, determining a symbol transition.
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