US 12,441,604 B2
Micro-electromechanical systems (MEMS) device with outgas layer
Fan Hu, Taipei (TW); Wen-Chuan Tai, Hsinchu (TW); Li-Chun Peng, Hsin-Chu (TW); Hsiang-Fu Chen, Zhubei (TW); Ching-Kai Shen, Zhubei (TW); Hung-Wei Liang, New Taipei (TW); and Jung-Kuo Tu, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jun. 8, 2022, as Appl. No. 17/835,175.
Prior Publication US 2023/0399226 A1, Dec. 14, 2023
Int. Cl. B81B 7/00 (2006.01); B81C 3/00 (2006.01)
CPC B81B 7/008 (2013.01) [B81C 3/001 (2013.01); B81B 2203/033 (2013.01); B81B 2207/015 (2013.01); B81C 2201/013 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for forming an integrated chip, the method comprising:
etching a capping layer with a first etching process to form a first recess in the capping layer, wherein the first recess is delimited by a first lower surface of the capping layer and a first pair of sidewalls of the capping layer;
depositing a first outgas layer on the first lower surface of the capping layer, the first outgas layer having a first thickness;
forming a masking layer on the first outgas layer and directly over the first lower surface of the capping layer;
etching the first outgas layer with a second etching process and with the masking layer in place to remove the first outgas layer from a portion of the capping layer, wherein the outgas layer remains on the first lower surface of the capping layer after the second etching process;
etching the capping layer with a third etching process to form a second recess in the capping layer laterally spaced apart from the first recess by the capping layer, wherein the second recess is delimited by a second lower surface of the capping layer and a second pair of sidewalls of the capping layer; and
depositing a second outgas layer on the second lower surface of the capping layer, the second outgas layer having a second thickness different than the first thickness.