CPC H10N 70/021 (2023.02) [H10B 63/84 (2023.02); H10N 70/063 (2023.02); H10N 70/066 (2023.02); H10N 70/068 (2023.02); H10N 70/841 (2023.02); H10N 70/8833 (2023.02)] | 20 Claims |
1. A method of fabricating a resistive random access memory cell, comprising:
forming a stacked layer alternately stacked by a plurality of first conductive layers and a plurality of first sacrificial layers on a first dielectric layer;
patterning the stacked layer to form a patterned stacked layer;
forming a second sacrificial layer around the patterned stacked layer;
forming an opening passing through the plurality of first conductive layers and the plurality of first sacrificial layers in the patterned stacked layer;
forming a second conductive layer in the opening, wherein the second conductive layer and the plurality of first conductive layers form a first electrode layer;
removing the plurality of first sacrificial layers and the second sacrificial layer;
forming a variable resistance layer and an oxygen reservoir layer on a surface of the first electrode layer and a top surface of the first dielectric layer;
patterning the oxygen reservoir layer to form a patterned oxygen reservoir layer and expose the variable resistance layer;
forming a second dielectric layer on the variable resistance layer and the patterned oxygen reservoir layer; and
forming a second electrode in the second dielectric layer, wherein the second electrode covers a top surface and an upper sidewall of the patterned oxygen reservoir layer.
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