CPC H10K 59/1213 (2023.02) [H10K 59/1216 (2023.02); H10K 59/122 (2023.02); H10K 59/131 (2023.02)] | 20 Claims |
1. A display substrate, comprising:
a base substrate;
a pixel circuit layer, located on the base substrate and comprising a plurality of pixel driving circuits; and
an anode layer, located at a side of the pixel circuit layer away from the base substrate and comprising a plurality of anodes,
wherein the plurality of pixel driving circuits are electrically connected with the plurality of anodes in one-to-one correspondence, each of the plurality of pixel driving circuits comprises a compensating thin film transistor and a driving thin film transistor, a source electrode of the compensating thin film transistor is connected with a drain electrode of the driving thin film transistor, and a drain electrode of the compensating thin film transistor is connected with a gate electrode of the driving thin film transistor; and
the plurality of pixel driving circuits comprise a first pixel driving circuit and a second pixel driving circuit which are adjacently arranged, and an orthographic projection of a channel region of the compensating thin film transistor in the first pixel driving circuit on the base substrate and an orthographic projection of a channel region of the compensating thin film transistor in the second pixel driving circuit on the base substrate both overlap with an orthographic projection of the anode corresponding to the first pixel driving circuit on the base substrate.
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