| CPC H10B 63/845 (2023.02) [H10B 61/22 (2023.02); H10B 63/34 (2023.02); H10N 50/01 (2023.02); H10N 70/066 (2023.02)] | 10 Claims |
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1. A method for manufacturing a memory device, comprising:
providing a stacked structure disposed on a substrate, the stacked structure comprising a plurality of sacrificial layers and a plurality of insulating layers alternately stacked along a first direction;
forming a plurality of openings passing through the stacked structure;
removing portions of the sacrificial layers to form a plurality of grooves between the sacrificial layers, the insulating layers and the openings;
forming a channel material layer in the grooves, wherein the channel material layer includes a first side and a second side, and the first side and the second side are opposite to each other;
forming a vertical hole extending along the first direction on the first side of the channel material layer;
filling a conductive material in the vertical hole to form a first conductive pillar;
forming an extension hole extending along the first direction on the second side of the channel material layer, and the channel material layer becomes a channel layer;
sequentially filling a memory material and a conductive material in the extension hole to form a memory structure and a second conductive pillar, respectively, wherein the memory structure surrounds the second conductive pillar and comprises a resistive memory material; and
removing the sacrificial layers and filling a conductive material at positions where the sacrificial layers are removed, to form a plurality of conductive layers.
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