US 12,114,512 B2
Semiconductor device and manufacturing method thereof
Chien-Min Lee, Hsinchu County (TW); Tung-Ying Lee, Hsinchu (TW); Cheng-Hsien Wu, Hsinchu (TW); Xinyu Bao, Fremont, CA (US); Hengyuan Lee, Hsinchu County (TW); and Ying-Yu Chen, Yilan (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jul. 25, 2023, as Appl. No. 18/358,035.
Application 18/358,035 is a continuation of application No. 17/241,071, filed on Apr. 27, 2021, granted, now 11,805,661.
Claims priority of provisional application 63/070,833, filed on Aug. 27, 2020.
Prior Publication US 2023/0371280 A1, Nov. 16, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H10B 63/00 (2023.01); H10N 70/00 (2023.01); H10N 70/20 (2023.01)
CPC H10B 63/24 (2023.02) [H10B 63/80 (2023.02); H10N 70/011 (2023.02); H10N 70/231 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A device, comprising:
a switch layer located in between two conductive layers, wherein the switch layer comprise a ternary GeCTe material, the ternary GeCTe material substantially consists of germanium, carbon, and tellurium, and is free of Selenium (Se), and in the ternary GeCTe material, a content of carbon is in a range from 10 to 30 atomic percent and a content of germanium is in a range from 10 to 65 atomic percent.