US 12,114,509 B2
FeRAM decoupling capacitor
Tzu-Yu Chen, Kaohsiung (TW); Kuo-Chi Tu, Hsinchu (TW); Fu-Chen Chang, New Taipei (TW); Chih-Hsiang Chang, Taichung (TW); and Sheng-Hung Shih, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Apr. 4, 2022, as Appl. No. 17/712,495.
Application 17/712,495 is a division of application No. 16/780,418, filed on Feb. 3, 2020, granted, now 11,296,099.
Claims priority of provisional application 62/881,133, filed on Jul. 31, 2019.
Prior Publication US 2022/0231034 A1, Jul. 21, 2022
Int. Cl. H01L 21/00 (2006.01); G11C 11/22 (2006.01); H01L 49/02 (2006.01); H10B 53/10 (2023.01); H10B 53/30 (2023.01)
CPC H10B 53/30 (2023.02) [G11C 11/221 (2013.01); H01L 28/56 (2013.01); H01L 28/75 (2013.01); H10B 53/10 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
depositing a bottom electrode layer over and coupled to a first metallization layer;
depositing a first insulating layer over the bottom electrode layer, the first insulating layer comprising a ferroelectric insulating material;
depositing a top electrode layer over the first insulating layer; and
separating the bottom electrode layer, the first insulating layer, and the top electrode layer into a plurality of capacitors, wherein the step of separating includes
patterning the top electrode layer in a first patterning step,
forming spacers on sidewalls of the patterned top electrode layer,
after forming the spacers, patterning the first insulating layer and the bottom electrode layer in a second patterning step, different from the first patterning step,
each of the capacitors comprising a bottom electrode, a ferroelectric insulator, and a top electrode.