CPC H10B 43/30 (2023.02) [H01L 21/31111 (2013.01); H01L 28/00 (2013.01); H01L 29/66833 (2013.01); H01L 29/792 (2013.01); H10B 43/27 (2023.02)] | 20 Claims |
1. An integrated chip, comprising:
a substrate including a protrusion region, the protrusion region having an upper surface and a sidewall; and
a gate electrode separated from the protrusion region by way of a tunnel dielectric layer; and
wherein the tunnel dielectric layer has different thicknesses over the protrusion region such that the tunnel dielectric layer has a first thickness measured along a first direction normal to the sidewall of the protrusion region and a corresponding sidewall of the tunnel dielectric layer, and has a second thickness measured along a second direction normal to an upper surface of the protrusion region and a corresponding upper surface of the tunnel dielectric layer, the second thickness being less than the first thickness, and wherein the first direction is perpendicular to the second direction.
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