US 12,114,501 B2
Vertical semiconductor device and method for fabricating the same
Jin-Ha Kim, Icheon (KR)
Assigned to SK hynix Inc., Icheon (KR)
Filed by SK hynix Inc., Icheon (KR)
Filed on May 15, 2023, as Appl. No. 18/317,692.
Application 18/317,692 is a continuation of application No. 17/585,133, filed on Jan. 26, 2022, granted, now 11,690,225.
Application 17/585,133 is a continuation of application No. 16/842,141, filed on Apr. 7, 2020, granted, now 11,271,008, issued on Mar. 8, 2022.
Claims priority of application No. 10-2019-0156872 (KR), filed on Nov. 29, 2019.
Prior Publication US 2023/0292513 A1, Sep. 14, 2023
Int. Cl. H10B 43/27 (2023.01); H01L 21/28 (2006.01); H01L 23/522 (2006.01); H01L 23/532 (2006.01); H01L 29/08 (2006.01)
CPC H10B 43/27 (2023.02) [H01L 23/5226 (2013.01); H01L 23/53271 (2013.01); H01L 23/53295 (2013.01); H01L 29/0847 (2013.01); H01L 29/40117 (2019.08)] 14 Claims
OG exemplary drawing
 
1. A method for fabricating a semiconductor device, comprising:
forming a first multi-layer stack including liner layers and a source sacrificial layer over a lower structure;
forming a second multi-layer stack including dielectric layers and sacrificial layers over the first multi-layer stack;
forming a vertical contact recess extending through the second multi-layer stack and the source sacrificial layer;
replacing the source sacrificial layer with a source contact layer;
replacing the sacrificial layers with conductive layers;
forming a seed layer on a sidewall of the vertical contact recess to seal the conductive layers;
forming a carbon-containing spacer on the seed layer; and
forming a source contact plug in the vertical contact recess.