US 12,114,494 B2
3D memory semiconductor device and structure
Zvi Or-Bach, Haifa (IL); Jin-Woo Han, San Jose, CA (US); and Eli Lusky, Ramat Gan (IL)
Assigned to Monolithic 3D Inc., Klamath Falls, OR (US)
Filed by Monolithic 3D Inc., Klamath Falls, OR (US)
Filed on Aug. 30, 2021, as Appl. No. 17/461,075.
Application 17/461,075 is a continuation in part of application No. 16/483,431, granted, now 11,152,386, previously published as PCT/US2018/016759, filed on Feb. 3, 2018.
Claims priority of provisional application 62/625,961, filed on Feb. 2, 2018.
Claims priority of provisional application 62/539,054, filed on Jul. 31, 2017.
Claims priority of provisional application 62/531,880, filed on Jul. 13, 2017.
Claims priority of provisional application 62/523,760, filed on Jun. 22, 2017.
Claims priority of provisional application 62/517,959, filed on Jun. 11, 2017.
Claims priority of provisional application 62/501,136, filed on May 4, 2017.
Claims priority of provisional application 62/488,757, filed on Apr. 22, 2017.
Claims priority of provisional application 62/484,284, filed on Apr. 11, 2017.
Claims priority of provisional application 62/473,308, filed on Mar. 17, 2017.
Claims priority of provisional application 62/468,372, filed on Mar. 8, 2017.
Claims priority of provisional application 62/454,785, filed on Feb. 4, 2017.
Prior Publication US 2022/0005821 A1, Jan. 6, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H10B 41/27 (2023.01); H10B 43/27 (2023.01)
CPC H10B 41/27 (2023.02) [H10B 43/27 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A 3D memory device, the device comprising:
a first vertical pillar, said first vertical pillar comprises a transistor source; and
a second vertical pillar, said second vertical pillar comprises a transistor drain,
wherein said first vertical pillar and said second vertical pillar each comprises a source or a drain for a first plurality of self-aligned overlaying horizontally-oriented memory transistors,
wherein at least of one of said first plurality of self-aligned overlaying horizontally-oriented memory transistors is disposed between said first vertical pillar and said second vertical pillar,
wherein said first plurality of self-aligned overlaying horizontally-oriented memory transistors each comprise a self-aligned gate,
wherein each self-aligned gate is disposed atop of a self-aligned underlying gate,
wherein each of said first plurality of self-aligned overlaying horizontally-oriented memory transistors comprises a self-aligned channel region, and
wherein at least two of the self-aligned channel region of said first plurality of self-aligned overlaying horizontally-oriented memory transistors comprise direct connection.