US 12,114,490 B2
Semiconductor device and method of forming the same
Naoyoshi Kobayashi, Higashihiroshima (JP); and Tsuyoshi Tomoyama, Higashihiorshima (JP)
Assigned to MICRON TECHNOLOGY, INC., Boise, ID (US)
Filed by MICRON TECHNOLOGY, INC., Boise, ID (US)
Filed on Dec. 21, 2021, as Appl. No. 17/558,323.
Prior Publication US 2023/0200058 A1, Jun. 22, 2023
Int. Cl. H10B 12/00 (2023.01)
CPC H10B 12/50 (2023.02) [H10B 12/09 (2023.02); H10B 12/315 (2023.02); H10B 12/34 (2023.02); H10B 12/488 (2023.02)] 4 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a substrate;
a memory cell region provided over the substrate;
a peripheral region provided over the substrate and adjacent to the memory cell region;
a plurality of word-lines extending in parallel across the memory cell region and the peripheral region;
a first insulating film covering top surfaces of the plurality of word-lines in each of the memory cell region and the peripheral region and covering side surfaces of upper portions of the plurality of word-lines in the peripheral region without covering side surfaces of the upper portions of the plurality of word-lines in the memory cell region; and
a third insulating film between the first insulating film and the top surfaces of the plurality of word-lines in the memory cell region.