US 12,114,485 B2
Semiconductor structure and method for manufacturing same
Qinghua Han, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Anhui (CN)
Filed on Feb. 11, 2022, as Appl. No. 17/669,573.
Application 17/669,573 is a continuation of application No. PCT/CN2021/117284, filed on Sep. 8, 2021.
Claims priority of application No. 202110808697.5 (CN), filed on Jul. 16, 2021.
Prior Publication US 2023/0020711 A1, Jan. 19, 2023
Int. Cl. H10B 12/00 (2023.01); H01L 29/10 (2006.01); H01L 29/423 (2006.01); H01L 29/786 (2006.01)
CPC H10B 12/482 (2023.02) [H01L 29/1041 (2013.01); H01L 29/42392 (2013.01); H01L 29/78696 (2013.01); H10B 12/30 (2023.02); H10B 12/488 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a base;
a bit line, located on the base; and
a semiconductor channel, located on a surface of the bit line, wherein in a direction from the base to the bit line, the semiconductor channel comprises a first doped region, a channel region, and a second doped region that are sequentially arranged, wherein the first doped region contacts the bit line, and the first doped region, the channel region, and the second doped region are doped with first-type doped ions, the channel region is further doped with second-type doped ions, enabling a concentration of majority carriers in the channel region to be less than concentrations of majority carriers in the first doped region and the second doped region, the first-type doped ions being one of N-type ions or P-type ions, and the second-type doped ions being the other of N-type ions or P-type ions.