US 12,114,484 B2
Buried bit line structure, manufacturing method thereof, and semiconductor structure
Wei Feng, Hefei (CN); Jingwen Lu, Hefei (CN); Bingyu Zhu, Hefei (CN); and Zhaopei Cui, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Feb. 11, 2022, as Appl. No. 17/650,702.
Application 17/650,702 is a continuation of application No. PCT/CN2021/116915, filed on Sep. 7, 2021.
Claims priority of application No. 202110862614.0 (CN), filed on Jul. 29, 2021.
Prior Publication US 2023/0032351 A1, Feb. 2, 2023
Int. Cl. H01L 27/108 (2006.01); H10B 12/00 (2023.01)
CPC H10B 12/482 (2023.02) [H10B 12/30 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A method of manufacturing a buried bit line structure, comprising:
providing an initial structure, the initial structure comprising a base and a protective layer provided on the base, and the base comprising active region structures and a dielectric layer, and a top surface of the active region structures is flush with a top surface of the dielectric layer;
forming an initial bit line trench in the initial structure, the initial bit line trench exposing the active region structures;
forming a conductive structure, the conductive structure being located at a bottom of the initial bit line trench and being at a preset distance from a bottom surface of the initial bit line trench;
forming a bit line contact structure, the bit line contact structure covering the conductive structure, and a top surface of the bit line contact structure being lower than the top surface of the active region structures; and
forming an insulation structure, the insulation structure covering the bit line contact structure, and a top surface of the insulation structure being flush with a top surface of the protective layer.