US 12,114,482 B2
Fabrication method of a memory and the memory
Kangshu Zhan, Hefei (CN); Jun Xia, Hefei (CN); Qiang Wan, Hefei (CN); Tao Liu, Hefei (CN); and Sen Li, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Aug. 16, 2021, as Appl. No. 17/403,809.
Application 17/403,809 is a continuation of application No. PCT/CN2021/101289, filed on Jun. 21, 2021.
Claims priority of application No. 202011622620.0 (CN), filed on Dec. 30, 2020.
Prior Publication US 2022/0208764 A1, Jun. 30, 2022
Int. Cl. H01L 29/78 (2006.01); H01L 21/265 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01); H10B 12/00 (2023.01)
CPC H10B 12/33 (2023.02) [H01L 21/26513 (2013.01); H01L 29/66757 (2013.01); H01L 29/78675 (2013.01); H10B 12/036 (2023.02); H10B 12/05 (2023.02)] 15 Claims
OG exemplary drawing
 
1. A fabrication method of a memory, comprising:
providing a substrate, the substrate comprising a central region and an edge region connected to the central region, a first contact structure being formed in the edge region, and the first contact structure being electrically connected to a wordline structure in the substrate;
forming a second contact structure on the edge region, the second contact structure being electrically connected to the first contact structure;
forming a capacitor structure on the central region, the capacitor structure being electrically connected to the wordline structure;
forming a third contact structure on the second contact structure, the third contact structure being electrically connected to the second contact structure; and
forming a transistor structure on the capacitor structure and the third contact structure, the transistor structure being electrically connected to the third contact structure, and an orthographic projection of the transistor structure on the substrate being at least partially coincident with orthographic projections of the capacitor structure and the third contact structure on the substrate.