US 12,114,480 B2
Method of making of plurality of 3D vertical logic elements integrated with 3D memory
H. Jim Fulford, Albany, NY (US); Mark I. Gardner, Albany, NY (US); and Partha Mukhopadhyay, Albany, NY (US)
Assigned to Tokyo Electron Limited, Tokyo (JP)
Filed by Tokyo Electron Limited, Tokyo (JP)
Filed on Dec. 21, 2021, as Appl. No. 17/558,490.
Prior Publication US 2023/0200052 A1, Jun. 22, 2023
Int. Cl. H01L 21/00 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H10B 12/00 (2023.01)
CPC H10B 12/31 (2023.02) [H01L 29/66666 (2013.01); H01L 29/7827 (2013.01); H10B 12/033 (2023.02); H10B 12/05 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A memory, comprising:
a first portion including a transistor, the first portion including:
a first source/drain structure extending horizontally;
a gate structure above the first source/drain structure and extending horizontally;
a second source/drain structure above the gate structure and extending horizontally, each of the structures separated from each other by at least one dielectric; and
a semiconductor material extending from the first source/drain structure to the second source/drain structure;
a second portion including a capacitor electrically coupled to and extending from the transistor.