US 12,114,479 B2
Three-dimensional memory arrays with layer selector transistors
Wilfred Gomes, Portland, OR (US); Mauro J. Kobrinsky, Portland, OR (US); Abhishek A. Sharma, Hillsboro, OR (US); Rajesh Kumar, Portland, OR (US); Kinyip Phoa, Beaverton, OR (US); Elliot Tan, Portland, OR (US); Tahir Ghani, Portland, OR (US); and Swaminathan Sivakumar, Beaverton, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jul. 6, 2021, as Appl. No. 17/368,329.
Application 17/368,329 is a continuation of application No. 16/689,789, filed on Nov. 20, 2019, granted, now 11,139,300.
Prior Publication US 2021/0335791 A1, Oct. 28, 2021
Int. Cl. H10B 12/00 (2023.01); G11C 5/06 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 27/06 (2006.01); H01L 29/786 (2006.01)
CPC H10B 12/31 (2023.02) [G11C 5/063 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 27/0688 (2013.01); H01L 29/78696 (2013.01); H10B 12/30 (2023.02)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) device, comprising:
an arrangement that includes two or more memory cells, a transistor, and a bitline; and
an interconnect structure,
wherein:
an individual memory cell of the arrangement includes an access transistor,
each of the transistor and the access transistor includes a first region and a second region, wherein one of the first region and the second region is a source region and another one of the first region and the second region is a drain region,
the first regions of the access transistors of the two or more memory cells of the arrangement are directly electrically connected to one another and to the bitline, and the bitline is directly electrically connected to the first region of the transistor, and
the second region of the transistor is directly electrically connected to the interconnect structure.