CPC H10B 12/30 (2023.02) [H10B 12/033 (2023.02)] | 17 Claims |
1. A semiconductor device, comprising:
a substrate comprising a memory array region and a peripheral region;
a first interlayer insulation layer and a second interlayer insulation layer, formed in the memory array region and the peripheral region of the substrate, the first interlayer insulation layer and the second interlayer insulation layer being arranged at intervals along a direction perpendicular to the substrate;
a columnar capacitor array, comprising columnar capacitors arranged at intervals, and the columnar capacitors being formed in the first interlayer insulation layer and the second interlayer insulation layer within the memory array region; and
a contact structure, formed in the first interlayer insulation layer and the second interlayer insulation layer within the peripheral region,
wherein the contact structure comprises a first contact structure and a second contact structure which are interconnected, the first contact structure or the second contact structure being interconnected by penetrating the first interlayer insulation layer or the second interlayer insulation layer,
wherein an intermediate metal layer is further formed on a side of the first interlayer insulation layer away from the substrate,
wherein a surface of the intermediate metal layer is flush with a surface of the first interlayer insulation layer, the first contact structure, the intermediate metal layer, the second contact structure being sequentially arranged in the direction perpendicular to the substrate, wherein the first contact structure and the second contact structure are interconnected through an intermediate metal layer, the first contact structure penetrating the first interlayer insulation layer for an upward connection to the intermediate metal layer, and the second contact structure penetrating the second interlayer insulation layer for a downward connection to the same intermediate metal layer.
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