US 12,114,474 B2
Integrated memory comprising secondary access devices between digit lines and primary access devices
Scott J. Derner, Boise, ID (US); and Charles L. Ingalls, Meridian, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jul. 29, 2022, as Appl. No. 17/877,628.
Application 17/877,628 is a continuation of application No. 17/324,976, filed on May 19, 2021, granted, now 11,450,668.
Application 17/324,976 is a continuation of application No. 16/514,693, filed on Jul. 17, 2019, granted, now 11,031,400, issued on Jun. 8, 2021.
Claims priority of provisional application 62/717,636, filed on Aug. 10, 2018.
Prior Publication US 2022/0367465 A1, Nov. 17, 2022
Int. Cl. G11C 11/24 (2006.01); G11C 11/4091 (2006.01); G11C 11/4094 (2006.01); H01L 29/78 (2006.01); H10B 12/00 (2023.01)
CPC H10B 12/00 (2023.02) [G11C 11/4091 (2013.01); G11C 11/4094 (2013.01); H01L 29/78 (2013.01); H01L 29/7827 (2013.01); H10B 12/50 (2023.02)] 28 Claims
OG exemplary drawing
 
1. An integrated assembly, comprising:
a first transistor extending in a first direction and having first and second source/drain regions;
a second transistor extending in a second direction oriented 90 degrees different from the first direction, the second transistor comprising a third source/drain region coupled with the first source/drain region of the first transistor; and
a charge-storage device coupled to the second source/drain region of the first transistor.