US 12,114,416 B2
Heat removal from silicon photonics chip using a recessed side-by-side thermal dissipation layout
Elad Mentovich, Tel Aviv (IL); Anna Sandomirsky, Nesher (IL); and Dimitrios Kalavrouziotis, Papagou (GR)
Assigned to MELLANOX TECHNOLOGIES, LTD., Yokneam (IL)
Filed by MELLANOX TECHNOLOGIES, LTD., Yokneam (IL)
Filed on Nov. 3, 2021, as Appl. No. 17/517,693.
Application 17/517,693 is a continuation in part of application No. PCT/GR2019/000032, filed on May 7, 2019.
Prior Publication US 2022/0061148 A1, Feb. 24, 2022
Int. Cl. H05K 1/02 (2006.01); H01L 23/367 (2006.01); H01L 23/38 (2006.01); H05K 1/18 (2006.01); H05K 3/30 (2006.01); H01L 23/13 (2006.01); H10N 10/13 (2023.01)
CPC H05K 1/0206 (2013.01) [H01L 23/367 (2013.01); H01L 23/38 (2013.01); H05K 1/0298 (2013.01); H05K 1/183 (2013.01); H05K 3/30 (2013.01); H01L 23/13 (2013.01); H10N 10/13 (2023.02)] 18 Claims
OG exemplary drawing
 
1. A semiconductor device assembly, comprising:
a multi-layer printed circuit board (PCB) comprising a lateral heat conducting path formed in a recessed area of the PCB;
a thermoelectric cooler (TEC) and a chip disposed on the PCB, side-by-side to one another within the recessed area, such that entire bottom surfaces of both the chip and the TEC are mounted directly on the lateral heat conducting path, wherein the TEC is configured to evacuate heat from the chip via the lateral heat conducting path, and to dissipate the evacuated heat via a first end of a heat sink in thermal contact with the TEC; and
packaged integrated circuitry (IC) disposed on an un-recessed area of the PCB, wherein the packaged IC is configured to dissipate heat via a second end of the heat sink that is in thermal contact with the packaged IC.