US 12,114,091 B2
Delta image sensor with digital pixel storage using different ramps for storage and comparison
Yingyun Zha, Regensdorf (CH); Roger Mark Bostock, Munsingen (CH); Jian Deng, Zurich (CH); and Yu Zou, Zurich (CH)
Assigned to Beijing Ruisizhixin Technology Co., Ltd, Beijing (CN); and AlpsenTek GmbH, Zurich (CH)
Appl. No. 18/002,798
Filed by Beijing RuisiZhixin Technology Co., Ltd., Beijing (CN); and Alpsentek GmbH, Zurich (CH)
PCT Filed Jun. 24, 2021, PCT No. PCT/EP2021/067338
§ 371(c)(1), (2) Date Dec. 21, 2022,
PCT Pub. No. WO2021/260105, PCT Pub. Date Dec. 30, 2021.
Claims priority of application No. 20182536 (EP), filed on Jun. 26, 2020.
Prior Publication US 2023/0247327 A1, Aug. 3, 2023
Int. Cl. H04N 25/771 (2023.01); G06F 7/02 (2006.01); H03M 1/12 (2006.01); H04N 25/40 (2023.01); H04N 25/47 (2023.01); H04N 25/703 (2023.01); H04N 25/766 (2023.01); H04N 25/772 (2023.01); H04N 25/78 (2023.01); H04N 25/79 (2023.01)
CPC H04N 25/771 (2023.01) [G06F 7/02 (2013.01); H03M 1/12 (2013.01); H04N 25/40 (2023.01); H04N 25/47 (2023.01); H04N 25/703 (2023.01); H04N 25/766 (2023.01); H04N 25/772 (2023.01); H04N 25/78 (2023.01); H04N 25/79 (2023.01)] 21 Claims
OG exemplary drawing
 
1. A delta image sensor comprising an arrangement of pixels and a plurality of acquisition circuits corresponding to at least one pixel of the arrangement of pixels and formed as part of an integrated circuit, each acquisition circuit including:
at least one sensor circuit comprising a photosensor configured to generate a sensor signal, VSIG, depending on a light signal illuminating the photosensor;
at least one analogue to digital conversion, A/D, circuit configured to generate a digital representation corresponding to a current sensor signal VSIG, wherein the A/D circuit is configured to use one of a plurality of ramps to generate the digital representation;
at least one digital storage circuit configured to store a representation of at least one digital signal generated using a storage ramp which constitutes one of the plurality of ramps, the representation corresponding to a previous sensor signal VSIG;
at least one digital comparison circuit configured to compare a level of the stored digital representation with the digital representation of the current sensor signal VSIG, being generated using a comparison ramp which constitutes a different one of the plurality of ramps than the storage ramp, to detect whether a changed level is present; and
at least one digital output circuit configured to generate an event output under a condition of the changed level.