US 12,114,089 B2
Pixel output parasitic capacitance reduction and predictive settling assist
Hai Yan, San Ramon, CA (US); and Chiajen Lee, Cupertino, CA (US)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Aug. 19, 2022, as Appl. No. 17/891,963.
Prior Publication US 2024/0064432 A1, Feb. 22, 2024
Int. Cl. H01L 27/146 (2006.01); H04N 25/75 (2023.01); H04N 25/77 (2023.01)
CPC H04N 25/77 (2023.01) [H01L 27/14636 (2013.01); H04N 25/75 (2023.01)] 20 Claims
OG exemplary drawing
 
1. A method of performing a row read operation of a pixel array of an image sensor, the pixel array including at least a first and a second pixel column, a first and a second pair of adjacent output signal lines (OSLs) positioned with or between and parallel to the first and second pixel columns, a first ground line interposed between the first and second pair of adjacent OSLs, a second ground line interposed between the first pixel column and the first pair of adjacent OSLs, and a third ground line interposed between the second pair of adjacent OSLs and the second pixel column, the method comprising:
applying an initial voltage to a first OSL of the first pair of adjacent OSLs during the row read operation;
subsequent to applying the initial voltage, configuring a voltage of the first OSL of the first pair of adjacent OSLs to float;
while the voltage of the first OSL of the first pair of adjacent OSLs floats, applying a signal transfer pulse to a first pixel of the first pixel column;
receiving a pixel output signal of the first pixel of the first pixel column on a second OSL of the first pair of adjacent OSLs; and
applying a low voltage signal to the first OSL of the first pair of adjacent OSLs during a pull-down time interval containing a falling edge of the signal transfer pulse.