CPC H04N 19/70 (2014.11) | 4 Claims |
1. A device comprising one or more processors configured to:
parse a zero four bits syntax element in a decoding capability information (DCI) raw byte sequence payload (RBSP) syntax structure, wherein the zero four bits syntax element is an unsigned integer using 4 bits;
parse a number syntax element in the DCI RBSP syntax structure, wherein the number syntax element plus 1 specifies a number of profile tier level syntax structures in a DCI network abstraction layer (NAL) unit;
parse a profile tier level syntax structure in the DCI RBSP syntax structure;
parse a general level idc syntax element in the profile tier level syntax structure; and
parse a general constraint information syntax structure in the profile tier level syntax structure,
wherein
the number syntax element is parsed immediately after the zero four bits syntax element is parsed,
the general constraint information syntax structure includes a plurality of flags imposing constraints, and
the general constraint information syntax structure is parsed after the general level idc syntax element is parsed in the profile tier level syntax structure.
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