CPC H04L 67/148 (2013.01) [H04L 63/0892 (2013.01); H04L 67/04 (2013.01); H04L 67/1095 (2013.01); H04L 67/1097 (2013.01); H04L 67/54 (2022.05)] | 20 Claims |
1. An apparatus comprising at least one processor and at least one memory, the at least one memory having computer-coded instructions stored thereon that, in execution with the at least one processor, cause the apparatus to:
establish a plurality of connection channels associated with a plurality of user data objects, each connection channel enabling access to functionality associated with a shared electronic data object via one of a plurality of computing devices;
detect, for a first user data object of the plurality of user data objects, a connection channel change associated with a first connection channel corresponding to a first computing device;
maintain, via at least one of the plurality of connection channels, access to the shared electronic data object during the connection channel change;
determine, based on the connection channel change, that a device capability is available; and
update, based on the connection channel change, the functionality associated with the shared electronic data object for at least one of the plurality of connection channels to enable use of the device capability.
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