| CPC H04L 49/9094 (2013.01) [H04L 49/109 (2013.01); H04L 49/3027 (2013.01); H04L 49/9021 (2013.01)] | 20 Claims |
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1. A method of operating a network on a chip, comprising:
receiving a first packet with a first output interface direction through a first master interface terminal in response to a clock signal;
receiving a second packet with a second output interface direction through a second master interface terminal in response to the clock signal;
storing the first packet and the second packet with corresponding buffer index queues in a buffer memory;
sequentially outputting at least one of the stored packets through a first slave interface terminal based on the buffer index queues in response to the clock signal when at least one of the first output interface direction or the second output interface direction indicates the first slave interface terminal; and
sequentially outputting at least one of the stored packets through a second slave interface terminal based on the buffer index queues in response to the clock signal when at least one of the first output interface direction or the second output interface direction indicates the second slave interface terminal.
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