US 12,113,721 B2
Network interface and buffer control method thereof
Nobuhiro Yokoi, Tokyo (JP); and Hiroka Ihara, Tokyo (JP)
Assigned to HITACHI, LTD., Tokyo (JP)
Filed by Hitachi, Ltd., Tokyo (JP)
Filed on Jun. 5, 2023, as Appl. No. 18/205,856.
Application 18/205,856 is a continuation of application No. 17/896,204, filed on Aug. 26, 2022, granted, now 11,700,214.
Claims priority of application No. 2022-048675 (JP), filed on Mar. 24, 2022.
Prior Publication US 2023/0328008 A1, Oct. 12, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H04L 49/9047 (2022.01); H04L 49/90 (2022.01)
CPC H04L 49/9052 (2013.01) [H04L 49/9084 (2013.01)] 8 Claims
OG exemplary drawing
 
1. A network interface comprising:
a processor;
a memory; and
a cache between the processor and the memory,
wherein the processor is configured to:
secure a plurality of buffers for storing transfer data in the memory, and
determine whether or not a buffer is required to be allocated for new transfer data based on an amount of buffer in use, and
a maximum value of the number of buffers capable of being used simultaneously in the plurality of buffers is set,
wherein the processor is configured to allocate a plurality of buffer groups in the memory,
wherein each of the plurality of buffer groups is composed of a plurality of buffers of the same size,
wherein the plurality of buffer groups have different buffer sizes from each other, and
wherein when a transfer data size is equal to or less than a maximum buffer size of the different buffer sizes, the processor is configured to select a buffer group having a minimum buffer size among buffer sizes equal to or greater than the transfer data size to store the transfer data.