CPC H04L 47/28 (2013.01) [G06N 20/00 (2019.01); H04W 28/06 (2013.01)] | 19 Claims |
1. An apparatus for wireless communication, the apparatus comprising:
a memory storing computer executable code; and
one or more processors coupled with the memory and configured to, individually or collectively, cause the apparatus to:
determine, based at least in part on one or more parameters, one or more time durations to buffer packets at a radio link control (RLC) layer and/or a packet data convergence protocol (PDCP) layer, the one or more time durations being different than a time duration of a configured timer for buffering the packets, wherein the one or more parameters comprise one or more lower layer block error rates (BLERs); and
buffer the packets for one of the determined one or more time durations.
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