US 12,113,712 B2
Dynamic network-on-chip throttling
Narendra Kamat, Austin, TX (US); Vydhyanathan Kalyanasundharam, Santa Clara, CA (US); Gregg Donley, Santa Clara, CA (US); and Ashwin Chincholi, Austin, TX (US)
Assigned to ADVANCED MICRO DEVICES, INC., Santa Clara, CA (US)
Filed by ADVANCED MICRO DEVICES, INC., Santa Clara, CA (US)
Filed on Sep. 25, 2020, as Appl. No. 17/032,054.
Prior Publication US 2022/0103481 A1, Mar. 31, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H04L 47/20 (2022.01); G06F 15/78 (2006.01); H04L 47/24 (2022.01); H04L 49/109 (2022.01)
CPC H04L 47/20 (2013.01) [G06F 15/7825 (2013.01); H04L 47/24 (2013.01); H04L 49/109 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of dynamic network-on-chip traffic throttling, the method comprising:
implementing a traffic throttling policy for a network-on-chip of a system-on-chip (SoC) in response to a predefined condition being met by sending an indication to a plurality of traffic generating agents of the SoC to implement the traffic throttling policy using an unrouted signal path between a mediator circuit of the network-on-chip and the plurality of traffic generating agents, wherein the unrouted signal path does not include one or more routing agents.