US 12,113,547 B2
Application of low-density parity-check codes with codeword segmentation
Santhosh K. Vanaparthy, Santa Clara, CA (US); and Ravi H. Motwani, Fremont, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Oct. 6, 2022, as Appl. No. 17/961,410.
Application 17/961,410 is a continuation of application No. 17/130,697, filed on Dec. 22, 2020, granted, now 11,515,891.
Prior Publication US 2023/0036512 A1, Feb. 2, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H03M 13/11 (2006.01); H03M 13/01 (2006.01); H03M 13/15 (2006.01); H03M 13/43 (2006.01)
CPC H03M 13/1137 (2013.01) [H03M 13/1157 (2013.01); H03M 13/015 (2013.01); H03M 13/1125 (2013.01); H03M 13/1575 (2013.01); H03M 13/43 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A low-density parity-check (LDPC) decoder circuit, comprising:
a segment calculator circuit to segment a codeword of length C bits into N non-overlapping segments of C/N bits, where N is an integer greater than one, and compute an expected error rate for the N non-overlapping segments; and
an error correction code (ECC) computation circuit having check nodes, the ECC computation circuit to perform check node computations, including to first perform decode computations for the N non-overlapping segments, on separate C/N bits at a time with the check nodes, including to adjust the decode computations based on the expected error rate for selected segments of the codeword, and then to perform decode computations for the C bits of the codeword together, based on the decode computations for the N non-overlapping segments.