a clock generator configured to generate an internal clock signal and a reset control signal based on an external clock signal, the internal clock signal being regularly toggled, the reset control signal being regularly toggled;

a random reset control signal generator configured to generate a random reset control signal based on the reset control signal, the random reset control signal being irregularly toggled;

a first capacitor array including a plurality of capacitors, and configured to generate a first summation voltage based on a first reference voltage and a second reference voltage, the plurality of capacitors in the first capacitor array being connected to a first summation node and having different capacitances, the first summation voltage corresponding to a first input digital signal;

a first reset circuit configured to initialize the first summation node based on the random reset control signal and a change in the first input digital signal; and

an output buffer configured to generate a first analog output voltage by buffering the first summation voltage,

wherein the capacitor digital-to-analog converter is configured to operate in a reset phase for initializing the first summation node, and during the reset phase, a value of the first input digital signal sequentially increases based on the internal clock signal.