US 12,113,538 B2
Error detection and compensation for a multiplexing transmitter
Naga Rajesh Doppalapudi, Santa Clara, CA (US); and Echere Iroaga, Mountain View, CA (US)
Assigned to MACOM Technology Solutions Holdings, Inc., Lowell, MA (US)
Filed by MACOM Technology Solutions Holdings, Inc., Lowell, MA (US)
Filed on Sep. 21, 2020, as Appl. No. 17/027,539.
Application 17/027,539 is a division of application No. 16/143,493, filed on Sep. 27, 2018, granted, now 10,784,845.
Prior Publication US 2021/0006238 A1, Jan. 7, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. H04B 17/15 (2015.01); H03K 5/05 (2006.01); H03K 5/135 (2006.01); H03K 5/156 (2006.01); H03K 5/00 (2006.01)
CPC H03K 5/1565 (2013.01) [H03K 5/05 (2013.01); H03K 5/135 (2013.01); H04B 17/15 (2015.01); H03K 2005/00286 (2013.01)] 42 Claims
OG exemplary drawing
 
1. A system for reducing error associated with a transmitter, comprising:
an error detector circuit configured to measure a quadrature error for a clock associated with the transmitter to generate first error detector information based on a first clock pattern for a first output generated by the transmitter in response to a defined bit pattern, and generate second error detector information based on a second clock pattern for a second output generated by the transmitter in response to an inverted version of the defined bit pattern, wherein the error detector circuit is further configured to determine a first average value of the first error detector information and a second average value of the second error detector information, determine a differential average value of the first average value and the second average value based on a comparison of the first average value to the second average value, and determine an error detector output based on the differential average value; and
a quadrature error correction circuit configured to adjust the clock associated with the transmitter based on the error detector output.