US 12,113,537 B1
Pipeline clock driving circuit, computing chip, hashboard, and computing device
Nan Li, Guangdong (CN); Haifeng Guo, Guangdong (CN); Zhijun Fan, Guangdong (CN); and Lianhua Duan, Guangdong (CN)
Assigned to SHENZHEN MICROBT ELECTRONICS TECHNOLOGY CO., LTD., Shenzhen (CN)
Appl. No. 18/704,562
Filed by SHENZHEN MICROBT ELECTRONICS TECHNOLOGY CO., LTD., Guangdong (CN)
PCT Filed Jan. 12, 2024, PCT No. PCT/CN2024/072007
§ 371(c)(1), (2) Date Apr. 25, 2024,
PCT Pub. No. WO2024/160037, PCT Pub. Date Aug. 8, 2024.
Claims priority of application No. 202310130858.9 (CN), filed on Feb. 2, 2023.
Int. Cl. H03K 5/00 (2006.01); H03K 3/027 (2006.01); H03K 5/13 (2014.01); H03K 5/15 (2006.01)
CPC H03K 5/1508 (2013.01) [H03K 3/027 (2013.01); H03K 5/13 (2013.01); H03K 5/15 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A pipeline clock driving circuit, configured to provide a pulse clock signal for a pipeline comprising a plurality of operation stages, the pipeline clock driving circuit comprising:
a plurality of stages of clock driving circuits, wherein each stage of clock driving circuit is configured to provide the pulse clock signal to a corresponding operation stage of the plurality of operation stages of the pipeline; and
a clock source, coupled to an input of a first-stage clock driving circuit and configured to provide a basic clock signal, wherein
an input of each stage of clock driving circuit other than the first-stage clock driving circuit in the plurality of stages of clock driving circuits is coupled to an output of a previous-stage clock driving circuit, and
wherein each stage of clock driving circuit comprises:
a trigger, coupled to an input of a current-stage clock driving circuit;
a delay module, comprising a first delay sub-module, wherein the first delay sub-module is coupled to an output of the trigger and delays a pulse signal output by the trigger, and feeds a delayed pulse signal back to the trigger as a feedback pulse signal; and
a combinational logic module, coupled to outputs of the trigger and the first delay sub-module, the combinational logic module performing a combinational logic operation on the pulse signal output by the trigger and the feedback pulse signal output by the first delay sub-module to generate the pulse clock signal to be provided to a corresponding operation stage of the pipeline, and
in each stage of clock driving circuit other than a last-stage clock driving circuit in the plurality of stages of clock driving circuits, the delay module further comprises a second delay sub-module, and the second delay sub-module is coupled to the output of the trigger and delays the pulse signal output by the trigger, and outputs the delayed pulse signal to a next-stage clock driving circuit as a clock driving signal.