CPC H03K 3/011 (2013.01) [H03F 1/08 (2013.01); H03K 5/26 (2013.01); H03K 17/56 (2013.01)] | 20 Claims |
1. A pseudo resistor, comprising:
a first transistor, including a first terminal, a second terminal and a control terminal; and
a second transistor of same type of transistor as the first transistor, including a first terminal, a second terminal and a control terminal, the first terminal of the second transistor being coupled to the first terminal of the first transistor and forming a first common node, the control terminal of the first transistor being coupled to the control terminal of the second transistor and forming a second common node; and
an adder, coupled between the first common node and the second common node, configured to receive an adjustment voltage and generating a bias voltage controlling the first and second transistors, the adjustment voltage corresponding to an output signal coupled to the second terminal of the second transistor, wherein the output signal is generated based on an input signal coupled to the second terminal of the first transistor.
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